1. Field of the Invention
The present invention relates to a standard cell, a standard cell library, a semiconductor device, and a placing method of the same.
2. Description of the Related Art
In conventional standard cell semiconductor devices, a number of standard cells are supposed to have substantially the same height so that they can be placed without a gap, i.e., with high density. Further, the cells have the same height of a border line between a P-well region and an N-well region (hereinafter referred to as a well border line height) so that an area efficiency of each individual standard cell is increased and a design rule error does not occur when the cells are placed.
FIG. 31 is a diagram illustrating an exemplary placement of a conventional standard cell semiconductor device. 100 to 138 each represent a standard cell, and h100 represents a height of the standard cell. hP represents a height of a P-well region, and hN represents a height of an N-well region. In FIG. 31, the standard cells have the same set height h100, the P-well regions of the standard cells have the same set height hP of the border line, and the N-well regions of the standard cells have the same set height hN.
In such a conventional standard cell type, when a semiconductor integrated circuit having standard cells having different heights is realized, the standard cells are divided into blocks or columns, in each of which standard cells have the same height. This technique is described in, for example, JP 2004-79702 A.
Also, when a transistor is optimized by, for example, modifying the diffusion layer into a double-layer structure within standard cells, the standard cells have the same height and the well border lines within the standard cells have the same height. This technique is disclosed in, for example, Bu-Yeol Lee and two other persons, “Low-power CMOS Standard Cell Library”, winning the IP award in the 1st LSI IP Design Award (1999), which was found on the Internet on Jun. 3, 2004: URL: http//ne.nikkeibp.co.jp/IPJapan/ipaward/990618ipa8.html.
However, in the case where standard cells have the same high height and the well border lines thereof have the same height, when a transistor having a low level of performance (i.e., a so-called small-size transistor) is realized, a useless region may occur and therefore the area efficiency may be reduced. FIG. 32 is a diagram illustrating a specific example of this situation, i.e., a standard cell which has a CMOS structure employing a small-size transistor and has a low level of area efficiency. In FIG. 32, the standard cell comprises a P-type diffusion region P2 for forming a P-type transistor in an N-well region N1 and an N-type diffusion region N2 for forming an N-type transistor in a P-well region P1. In FIG. 32, 140 indicates gate connection, and WP and WN, and LP and LN indicate transistor dimensions. WP is a width in a height direction of the P-type transistor, WN is a width in a height direction of the N-type transistor, LP is a gate length of the P-type transistor, and LN is a gate length of the N-type transistor. W103 indicates an interval between the P-type diffusion region P2 and the N-type diffusion region N2. When the low-performance transistors are provided in the standard cell having the high cell height in this manner, a useless region corresponding to the interval W103 occurs and therefore the area efficiency is reduced. Therefore, when a low-performance transistor (i.e., a so-called small-size transistor) is employed, it is preferable in terms of efficiency that a standard cell having a low cell height be designed.
Conversely, when standard cells have the same low height and the well border lines thereof have the same height, a plurality of transistors need to be provided so that these are connected in parallel in order that a high-performance transistor (i.e., a so-called large-size transistor) can be realized in a standard cell having a low cell height. When an attempt is made to provide a large-size transistor in a standard cell having a low height in this manner, the standard cell has a longer width in a traverse direction (perpendicular to the height direction) than in the height direction, and a gap region occurs at a border between P and N wells, resulting in a low level of area efficiency. As a specific example of this, FIG. 33 illustrates a standard cell which has a low cell height and in which a high-performance CMOS transistor is provided. In the standard cell of FIG. 33, a P-type diffusion region P2 is provided in an N-well region N1 and an N-type diffusion region N2 is provided in a P-well region P1, so that a P-type transistor and an N-type transistor are provided. W101 indicates a gap occurring between an upper end of the N-well region N1 and the P-type diffusion region P2, W100 indicates a gap occurring between the P-type diffusion region P2 and the N-type diffusion region N2, and W102 indicates a gap between the N-type diffusion region N2 and a lower end of the P-well region P1. 140 indicates a wiring line which is connected to gates. When the transistor is extended in the traverse direction in this manner, it is necessary to provide an enlarged region corresponding to the distance W101 from the upper end of the N-well region N1 to the P-type diffusion region P2, the distance W102 from the lower end of the P-well region P1 to the N-type diffusion region N2, and the distance W100 of a diffusion region between the P and N wells P1 and N1, resulting in a reduction in the area efficiency of the transistor region. In addition, a transistor having a single gate has a higher current performance per unit length even if the transistor size is the same. Also, the area of a transistor having a single gate can be reduced since gate capacitance does not have a plurality of gate protrusions. Therefore, a standard cell having a high cell height can realize a higher-speed operation even if the transistor size is the same.
There is a lineup of standard cells having various logics (various combinations), including a logic in which P-channel transistors are connected in series, a logic in which N-channel transistors are connected in series, and the like. When transistors are connected in series, the performance of the transistors connected in series needs to be increased in order to obtain a response speed comparable to that of a single transistor. To achieve this, the transistor size needs to be increased. Therefore, when P-channel transistors are connected in series, the P-channel transistor size needs to be increased. When N-channel transistors are connected in series, the N-channel transistor size needs to be increased.
Therefore, in order to minimize the area of a standard cell, the height of a border between the P-well region and the N-well region needs to be changed among standard cells, depending on its application. However, a peripheral portion of the diffusion region is typically designed to be minimized so that the design rule is satisfied, assuming that the well regions of the same type are adjacent to each other, so that standard cells cannot be arranged so that different well regions are adjacent to each other without an increase in area of the peripheral region of the diffusion region. Thus, it is difficult to minimize the area of each standard cell.